High-Performance Integer Decompression Using SIMD Vector Instructions

Zigzag Decoding with AVX-512

Based on research by Arseny Kapoulkine

June 2026

02

What is Zigzag Encoding?

A compact variable-length encoding for signed integers

Key Properties of Zigzag Encoding

01

Signed Integer Mapping Transforms negative integers into positive space: 0→0, -1→1, 1→2, -2→3...
02

Variable-Length Efficiency Small-magnitude integers (common in real data) use fewer bytes
03

Wide Adoption Used in Protocol Buffers, FlatBuffers, and other serialization formats
04

Compute Challenge Decoding requires bit manipulation at scale — ideal for SIMD optimization

04

AVX-512 Optimization

16x parallelism with 512-bit vector registers

AVX-512 Decoding Implementation

zigzag_avx512.cpp

__m512i zigzag_decode(__m512i v) {
  __m512i sign = _mm512_and_si512(v, _mm512_set1_epi32(1));
  __m512i shifted = _mm512_srli_epi32(v, 1);
  __m512i negated = _mm512_sub_epi32(
    _mm512_setzero_si512(), sign);
  return _mm512_xor_si512(shifted, negated);
}

Process 16 integers simultaneously with a single instruction sequence

Decoding Algorithm Steps

1

Load Data

Load 16 × 32-bit integers into 512-bit AVX-512 register

→

2

Extract Sign

Isolate the lowest bit from each integer (sign bit in zigzag)

→

3

Shift Right

Logical right shift by 1 to get magnitude

→

4

Negate Sign

Create mask: 0 for positive, -1 for negative

→

5

XOR Merge

Combine shifted value with sign mask to restore original integer

Performance Comparison

1GB/s

Scalar

5.2GB/s

AVX2

12.8GB/s

AVX-512

Throughput on Intel Xeon with Cascade Lake architecture

Thank You

Accelerating data formats with modern CPU instructions

Source: zeux.io/2026/06/17/zigzag-decoding-avx512